In recent years, as the multimedia age in which technologies such as information, service and entertainment are united has come, need for transmitting mass-data at high speed is increasing more. With respect to bipolar transistors, it is also requested that bipolar transistors should become highly-efficient more than before.
In order to enable bipolar transistors to operate at high speed, bipolar transistors need a base layer which should be heavily-doped and which should reduce its film thickness.
However, when a base layer is formed by a prior-art ion implantation technique, due to channeling of implanted impurities, so far it has been difficult to realize a base layer having a base width less than 40 nm.
Therefore, as a step for solving this problem, a heterojunction bipolar transistor (Hetero Bipolar Transistor (hereinafter referred to as a “HBT”) which applies a technique for epitaxially depositing a mixed crystal layer of silicon-germanium (Si1-xGex (hereinafter referred to as a “SiGe)) on a silicon (Si) substrate receives a remarkable attention.
Further, in a bipolar transistor, as junction of a base layer becomes shallow, a concentration at which impurities are implanted into the base layer is caused to increase and there arises a problem of how to implant positive holes into the emitter.
However, because the above-mentioned SiGeHBT uses the SiGe layer having a band gap narrower than that of the silicon layer as a base region, a potential barrier is produced between the emitter and the base and implantation of positive holes into the emitter is decreased considerably.
Therefore, resistance of the base layer can be reduced by making the base layer become high in carrier concentration, and further a sufficiently large current amplification factor (hFE) can be obtained. As a consequence, it is possible to realize an excellent high-frequency characteristic while a sufficient withstanding high pressure can be maintained.
Moreover, when profile of germanium is given inclination, a time (τB) during which carriers travel through the base layer can be reduced, thereby making it possible to realize a high-speed bipolar transistor having an excellent high-frequency characteristic.
However, since the SiGe mixed crystal layer has different lattice constants of silicon and germanium and different coefficients of thermal expansion of silicon and germanium, stress is produced and there arises a problem in which a crystal defect which is what might be called a misfit dislocation occurs unavoidably.
This misfit dislocation strongly depends upon germanium concentration. Accordingly, if the germanium concentration is decreased, occurrence of crystal defect can be controlled. In this case, however, the effect for reducing the band gap width becomes unsatisfactory and hence the above-mentioned target performance of bipolar transistors cannot be obtained.
In the manufacturing process of the SiGeHBT, it is customary that an SiGe mixed crystal layer is epitaxially deposited on an active region separated by a separation silicon oxide layer formed by LOCOS (Local Oxidation: local silicon oxidation) and simultaneously a polycrystalline SiGe mixed crystal layer is formed on the separation silicon oxide layer.
In this case, since silicon and germanium are different in physical properties, and since stress is produced by LOCOS and stress is produced due to different coefficients of thermal expansion of the silicon oxide layer, silicon and germanium, misfit dislocation tends to occur.
FIG. 13 shows a cross-sectional view of a main portion of a semiconductor device in which an SiGe mixed crystal layer of the SiGeHBT is formed. In this case, on the surface of a single crystal silicon semiconductor substrate 21, there is formed a separation silicon oxide layer 1, formed by LOCOS for separating its active region or separating itself from other element, on which a deposited silicon oxide layer 2, formed by CVD (Chemical Vapor Deposition) technique, and a semiconductor layer 60 having an SiGe mixed crystal layer are deposited by low-temperature epitaxial technique.
The semiconductor layer 60 has a lamination layer structure of a trilayer-structure comprising a silicon buffer layer 61, an SiGe mixed crystal layer 62 and a silicon capping layer 63.
The silicon buffer layer 61 comprises a silicon epitaxial layer deposited in order to smoothen very small concavities and convexities produced on the N− expitaxial layer surface when an opening is formed through a base active region, for example, and a polycrystalline silicon layer deposited in order to form a seed (seed) layer required when a polycrystalline SiGe layer is formed on the separation silicon oxide layer 1 for separating the active region or separating itself from other semiconductor element.
The SiGe mixed crystal layer 62 that has been deposited on this silicon buffer layer 61 is deposited on the single crystal silicon layer of the semiconductor substrate 21 as an SiGe epitaxial layer and is also deposited on the separation silicon oxide layer 1 as a polycrystalline silicon layer.
The semiconductor layer 60 composed of a base in the bipolar transistor, and its portion extended on the separation silicon oxide layer 1 is used as a base electrode lead-out region.
This semiconductor layer 60 is deposited by reduced pressure chemical vapor deposition (RPCVD: Reduced Pressure Chemical Vapor Deposition). This semiconductor layer is deposited by this vapor-phase growth method as follows. While hydrogen gas is being introduced into a reaction furnace of a deposition apparatus, a semiconductor substrate is heated up to approximately 900° and baked by hydrogen for about 5 minutes. Thereafter, under the condition in which the hydrogen gas is being continuously introduced into the reaction furnace, a temperature at which the semiconductor substrate is heated is lowered up to approximately 710° C. to 660° C. and monosilane (SiH4) gas and germane (GeH4) gas which are raw material gases to deposit films and diborane (B2H6) gas which is incombustible gas are supplied to the reaction furnace to epitaxially deposit the target semiconductor layer.
A conventional procedure for depositing films according to a vapor-phase growth method will be described with reference to a time chart of FIG. 14.
First, as shown in FIG. 14A, in order that constant monosilane pressure may become 26.7 Pa (0.2 Torr) at a temperature of approximately 710° C. and at pressure approximately 10,666 Pa (80 Torr) within the reaction furnace, monisilane gas is supplied into the reaction furnace to deposit a silicon epitaxial film having a thickness of approximately 15 nm.
At that time, the buffer layer 61 is deposited on the separation silicon oxide layer 1 as the polycrystalline silicon layer simultaneously.
After the silicon buffer layer 61 has been deposited in this manner, a temperature within the reaction furnace is lowered up to approximately 660° C. and monosilane gas and germane gas are supplied into the reaction furnace while a flow rate of gas is being controlled in such a manner that a desired germanium concentration and a desired film thickness may be obtained. At that time, while a flow rate of diborane gas is being controlled in such a manner that a desired boron profile may be obtained, diborane gas is supplied into the reaction furnace. Thus, there is deposited the SiGe mixed crystal layer 62.
Subsequently, under the condition in which a temperature within the reaction furnace is held at approximately 680° C. and pressure within the reaction furnace is held at approximately 13,332 Pa (100 Torr), monosilane gas and diborane gas are supplied into the reaction furnace to deposit a boron-doped silicon epitaxial layer having a desired film thickness serving as the silicon capping layer 63.
FIG. 15 is a diagram showing magnitudes of shearing stresses obtained based upon differences of coefficients of thermal expansion of respective portions in the cross-section of the portion in which the semiconductor layer 60 is laminated from the single crystal silicon of the semiconductor substrate 21 to the silicon oxide by light and shade. As is clear from this diagram, the shearing stress is concentrated in the area encircled by a solid line a on the silicon oxide at its portion in which the semiconductor layer 60 is formed.
The present invention is to provide a vapor-phase growth method, a semiconductor manufacturing method and a semiconductor device manufacturing method in which the problem of the misfit dislocation produced in the vapor-phase growth method of the semiconductor layer including such SiGe mixed crystal layer can be solved and in which an SiGe epitaxial mixed crystal with excellent crystal quality can be obtained.
Further, in a method of manufacturing a semiconductor device including a bipolar transistor, for example, the present invention is to provide a semiconductor device manufacturing method in which a yield can be prevented from being lowered due to the above-mentioned misfit dislocation when a silicon-germanium epitaxial mixed crystal layer is used as the base of the semiconductor device.